1. Field of Invention
The present invention relates to a method and circuit for glitch-free changing of clocks having different phases. More particularly, the present invention relates to a method and circuit for glitch-free changing of clocks having different phases for a communication network system.
2. Description of Related Art
Generally, in an Ethernet communication network system, a receiver can usually only receive data streams transmitted from a transmitter while the clock of the transmitter is not transmitted to the receiver. If the receiver is prepared to sample the data streams transmitted from the transmitter, the clock of the receiver must be synchronized with the data. This is called the timing recovery.
The conventional method for executing the timing recovery uses a phase locked loop (PLL) for generating clocks with different phases at the receiver. For example, the PLL can generate 10, 20 or more clocks with different phases. By changing different clocks, the phases of the data streams are locked and tracked such that sampling clock are synchronized with the data, and therefore, the data streams can be read.
FIG. 1 shows a timing diagram for illustrating that the data are locked by one of the clocks with different phases. The clocks with different phases generated by the PLL include clocks PH_N, PH_N+1, PH_N+2, and PH_N+3 that all have the same frequency but are different in phase and sequence. Referring to FIG. 1, at time t1, when the receiver receives a data stream DATA, the data stream DATA must be locked and tracked using the clock PH_N. At time t2, the data stream DATA and the clock PH_N are out of phase, and therefore, the clock must be changed to PH_N+1. At time t3, the data stream DATA and the clock PH_N+1 are out of phase, and therefore, PH_N+2 must be used for locking and tracking the data stream DATA. At time t4, the data stream DATA and the clock PH_N+2 are out of phase, and therefore, the clock PH_N+3 must be used for locking and tracking the data stream DATA. Therefore, the receiver has to change its system clock phase in response to the phase change of the data stream DATA. For example, the clocks PH_N, PH_N+1, PH_N+2 and PH_N+3 are respectively used as the system clock CLK of the receiver at each time t1, t2, t3 and t4 for locking and tracking the data stream DATA.
FIG. 2 shows a timing diagram for changing the system clock. The operation of the conventional method is described using the process in which the system clock CLK is changed from the clock PH_N to PH_N+1 as an example. According to the conventional method, the clock PH_N or PH_N+1 is selected by determining whether the flag signal Flag_N or Flag_N+1 is enabled, e.g. at a high-level state). When the receiver detects that the phase of the data stream DATA has changed, the flag signal is changed correspondingly. For example, at time t, the flag signal Flag_N is changed from high to low while Flag_N+1 is changed from low to high. Therefore, the clock PH_N is used as the system clock CLK before time t, and the clock PH_N+1 is used as the system clock CLK after time t.
FIG. 3 shows a timing diagram for changing the system clock with glitch. Referring to FIG. 3, when the flag signals Flag_N and Flag_N+1 are changed at time t2 simultaneously, the clock PH_N is used as the system clock CLK before time t2, and the clock PH_N+1 is used as the system clock CLK after time t2. During the changing of the clocks, at time t2, the clock PH_N is high while the clock PH_N+1 is low. The system clock CLK is changing from low to high at time ti while changing from high to low at time t2, so an undesired glitch between the time interval t1 and t2 is produced. This glitch will interfere with data sampling.
FIG. 4 shows another timing diagram for changing the system clock with glitch. The glitch can occur when a circuit for example, is interfered by noise. The nonlinear signals result in that the two flag signals Flag_N and Flag_N+1 are not changing at the same time. In addition, the glitch can occur due to instability of the clocks. As shown in FIG. 4, the flag Flag_N is changing from high to low at time t2 but the flag Flag_N+1 is changing from low to high at a delayed time t3. The flag Flag_N and Flag_N+1 are not changing at the same time, resulting in a glitch occurring between time t1 and t2.
The glitch causes an unexpected pulse in the system clock CLK. If the pulse width of the glitch is too large, the glitch may be mistaken as the system clock CLK. The data stream DATA is then sampled according to the glitches, and thus a wrong sampling result is obtained. In addition, if the system clock includes glitches, the data stream cannot be correctly phase-locked and tracked, so as to fail reading data.
The conventional method for eliminating the glitch uses a low pass filter (LPF) consisting of capacitors for filtering the glitches in the system clock. However, if the period of the glitches is too long, larger capacitors are needed to filter the glitches, which increases the device area and cost. In addition, due to the capacitance effect, the rising and falling time of the system clock are increased, which limits the frequency of the system clock.